FIG. 1A is a schematic 100 of an Integrated Gate Bipolar Transistor (“IGBT”) 102 including parasitic capacitances CM coupled between the gate and the collector, CGE coupled between the gate and the emitter, and CCE coupled between the collector and the emitter.
FIG. 1B is a graph of values of the parasitic capacitances shown in FIG. 1A with respect to collector-emitter voltage, wherein CISS represents the sum of the CM and CGE capacitors, COSS represents the sum of the CM and CCE capacitors, and CM represents the Miller capacitor, which is highly non-linear due the gain of IGBT 102, as is known in the art. The values of capacitors CISS, COSS, and CM are relatively high for a low collector-emitter voltage, and rapidly decrease during an initial increase in the collector-emitter voltage, and then asymptotically approach a minimum value at high collector-emitter voltages.
FIG. 2A is a schematic diagram 200 of a prior art power switch including a high side driver 206 and a low side driver 204, a high side gate resistor RgHS and a low side gate resistor RgLS, as well as a high side power transistor T1 and a low side power transistor T2. Voltages VCE (collector-to-emitter voltage), VG (gate voltage), and VOUT, (voltage from the low side gate driver), and currents IG (gate current) and IC (collector current) associated with the low side driver are shown in FIG. 2A.
For a specified gate resistor, it takes a relatively long time to charge and discharge the parasitic capacitances shown in FIG. 1A. Therefore, the propagation delay of the power transistors shown in FIG. 2A is also relatively high. Portions of the propagation delay of the power transistors is referred to as “dead time” that must be considered in half-bridge applications in order to avoid cross-conduction. Large propagation delays for both the high side device and the low side device of a half-bridge power switch exist dominantly at turn-off when the collector-to-emitter voltage (“VCE”) or the drain-to-source voltage (“VDS”) is low. As depicted in FIG. 1B, in this case the Miller capacitance is very high. The long propagation delay causes a large dead time as the propagation delay at turn-on is short. This causes disadvantages in efficiency and precise timing.
One solution for addressing propagation delays is by a suitable selection of the gate resistors RgLS and RgHS. The lower the gate resistance, the shorter the propagation delay. However, the gate resistance also specifies switching speed. Hence, the selection of the gate resistor Rg is limited by other design constraints, such as dv/dt restrictions of Electro-Magnetic Interference (“EMI”) limitations.
FIG. 2B is a timing diagram associated with the power switch of FIG. 2A showing the VOUT, VG, IG, VCE, and IC waveforms for a given value of RgHS and RgLS. Also shown in FIG. 2B is the IOFF waveform, which is the turn off current.
FIG. 3A is a more detailed timing diagram associated with a turn-on phase of the low side of the power switch of FIG. 2A and FIG. 3B is a more detailed timing diagram associated with a turn-off phase of the low side of the power switch of FIG. 2A. The waveforms shown in FIGS. 3A and 3B include the gate voltage (VG), output voltage (VS), gate current (IG), collector current (IC), and energy losses (E). The time parameters along the horizontal time axis of these waveforms include: tTH (time when the threshold voltage is achieved), t1 (time when the Miller plateau starts), t2 (time when the tail begins in the turn-on mode or ends in the turn-off mode), and t3 (time when the Miller plateau finishes).
In the waveforms of FIGS. 3A and 3B, which show the energy losses (E), the energy consumed during the switching of the power transistors is labeled ESW, whereas the energy consumed by conduction is labeled ECOND. Note that the energy consumed during switching of the power transistors includes a spiked portion and a long “tail” portion. The elongated tail is visible in the clearly marked arrow portions of the output voltage (VS) waveforms. The energy losses indicated by the tail portion lead to large power switching losses.
It is thus an object of the present invention to reduce propagation delays and power switching losses during switching of power switches.